To reduce power consumption, some modern computing systems place the processor or processors in a lower power consuming or idle state. With the advent of multi-core processors, management of the power states of two or more cores becomes a more complex problem than for single core processors. The exit latency of a core's transition from an idle or low power state to a more active power state may hinder processor performance and power consumption. Exit latency related performance limitations may become apparent when a processor receives and services an interrupt. Further complexities may be introduced in managing the power states of a multi-core processor for which each core includes two or more logical processors for independently executing separate threads.
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